Some embodiments according to the invention are related to a logic chip and to a method and computer program for providing a configuration information for a configurable logic chip.
Some embodiments according to the invention are related to a logic chip, a logic system and a method and computer program for designing a logic chip.
Some embodiments according to the invention are related to efficient re-configurable on-chip buses.
Some embodiments according to the invention are related to further developments regarding efficient re-configurable on-chip buses.
Some embodiments according to the invention are related to efficient re-configurable on-chip buses for field programmable gate arrays (FPGAs).
Some embodiments according to the invention are related to details regarding a mapping of a so-called “ReCoBus” on a FPGA.
The design of logic circuits has been a challenging task. However, at present, the complexity of logic circuits, logic chips and logic systems is steadily increasing. This brings along significant challenges in the design of such logic circuits. Also, with increasing complexity of the logic circuits, it is getting more and more difficult to provide an efficient way of interconnecting different logic blocks.
Also, it is often desired to have a high flexibility regarding the configuration of a logic circuit, which flexibility may be desirable in some cases at design time and in some cases even at a run time. To summarize, the design of logic circuits brings along a plurality of challenges.
In the following, some aspects regarding the design of logic circuits will be described.
The article “Design of homogeneous communication infrastructures for partially re-configurable FPGAs” of J. Hagemeyer (published in: proceedings of the 2007 International Conference on Engineering of Re-configurable Systems and Algorithms, Las Vegas, USA, Jun. 25-28, 2007) describes the concept of dynamic re-configuration as a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. A communication infrastructure is described that enables data transfer between the hardware modules that are placed on the FPGA at run-time. A communication macro for Xilinx FPGAs is described that considers the special requirements of these systems. The approach described in said paper implements an infrastructure that allows free placement of hardware modules at run time. Methodologies like 2D-placement of modules can be implemented. A tool-flow is described that automatically generates the necessitated communication infrastructure for FPGAs of the Xilinx Virtex-E to Virtex-5 family.
Further details can be taken from the “development system reference guide”, published online by Xilinx, for example in chapters 4 and 5 thereof.
Further aspects regarding the configuration of FPGAs are, for example, described in the “Spartan-3 generation FPGA user guide”, published online by Xilinx under document number UG331. For example, in chapter 5 of said document, the use of configurable logic blocks is described. In chapter 12 of said document, the use of interconnects is described.
Also, further aspects regarding interconnects are described in the “product specification”, published online by Xilinx under document number DS312-2 (v3.7), for example on pages 65 to 67.
Further Conventional Concepts
In the following, some further conventional systems will be described.
Systems using FPGA resources in a time variant manner by exploiting partial reconfiguration have been presented in various academic publications. One important issue of this work is the interfacing of hardware accelerators to on-chip buses (OCBs) and to the static system containing typically a CPU, the memory, and the I/O interface modules. Existing approaches for on-chip communication are based on i) circuit switching techniques, ii) packet switching mechanisms, and iii) on-chip buses. In the following, we will present each class separately.
Circuit Switching
In the following, a so-called circuit switching will be described.
Circuit switching is a technique where physically wired links are established between two or more modules for a certain amount of time. Typically, these links are realized by more or less complex crossbar switches. The switching state of the switches may be controlled centralized by the static part of the system [UHB04] or distributed by some logic in the crossbar switches itself [ESS+96, Ali05].
In [UHB04], a system is presented where hardware modules (e.g., a dedicated accelerator or a control function) can be configured into predefined FPGA resource areas of fixed size called a slot. The communication is implemented through dedicated communication macros attached at the bottom of a module's slot. The communication macros have dedicated crossbar like switch resources combined with connection points on the left and right border each. These macros allow a circuit switching between the modules and a bridge that connects the module to the OCB that is based on segmented buses. The routing and therefore the control of the switch elements is determined by a centralized arbiter. This approach does not allow a direct connection to I/O-peripherals connected to the OCB. All I/O communication has to be implemented over the bridge by the CPU subsystem. The bridge concept necessitates a specialized module interface and furthermore a specialized driver interface for the CPU subsystem.
In [ESS+96, Ali05] a circuit switching architecture is presented where the switching state is determined by the crossbar switches themselves with respect to currently used routing resources. The approach necessitates fully equipped crossbars. As a consequence, the approach allows only a few modules to be integrated into a re-configurable system.
Both approaches do not allow a module to directly access any memory of the system. In addition, the large multiplexers necessitated for circuit switching allow only a very coarse-grained placement of modules. The large multiplexers have also significant propagation delays leading to decreased throughputs when using circuit switching.
Another approach [HSKB06] for two dimensional circuit switching is based on templates for turning, forking, crossing, or routing through a set of signals. By attaching these templates together through partial reconfiguration, it is possible to set a fixed routing path between some modules. This approach necessitates a significant amount of area on the FPGA around the modules in order to build the routing because there is no technique available to share the routing wires inside the templates for building multiple routing tracks. As modules are obstacles for this kind of routing, the area necessitated for routing cannot be used to implement the module's logic. This circuit switching technique necessitates online routing algorithms and also an online timing verification.
Packet Switching
In the following, the so-called packet switching will be described.
The motivation for packet switching comes from the ASIC domain where more and more functional units were integrated. In order to deal with multiple clock domains, modularity for IP-reuse, and in order to support parallelism in communication and computation, networks on a chip (NoC) [BM02] have been proposed. This was the motivation in [AB+05] to integrate a dynamic re-configurable network on an FPGA called a DyNoC. Here, a grid of routers that are arranged in a mesh structure is used for the communication among the re-configurable modules. Each data packet has a header containing the destination address that is specified by the horizontal and vertical coordinates of the target module. Therefore, each router can decide locally when to deliver a packet to an attached module or where to send the packet further. The routers are capable to deal with obstacles. However, the approach in [AB+05] demands a relatively fine grid of routers while the implementation revealed that the logic for a single router necessitates several hundreds or even thousands of look-up tables (depending on the supported packet sizes) in order to implement the routing logic. We can conclude that packet routing produces an enormous overhead when implemented on FPGAs.
Buses
In the following, some buses will be described.
Buses are the native way to link communicating modules together within a system-on-a-chip (SoC). All major FPGA vendors offer tools that allow easily to integrate a set of user-defined modules or IP cores into complete systems by the use of on-chip buses. Consequently, buses are good candidates for integrating also partial re-configurable modules into a system at runtime. Most work [WP04], [KJdlTR05], [KPR04], [BMG06], and [PdMM+02] done in this field is based on older Xilinx Virtex FPGA architectures that provide wires that span over the complete horizontal width of the devices and that can be used to build buses with tristate drivers. However, newer FPGA architectures have no support for tristate wires and none of these approaches deal efficiently with dedicated signals, e.g., interrupt lines and chip select signals.
In [WP04], [KD06b] and [KD06a], systems are proposed where fixed resource areas with also fixed connection points to a bus interface are used for the integration of partially re-configurable modules into a runtime system. The main drawback of this solution is that all modules have to fit into such a resource area and that the resource areas could not be shared by multiple modules, even if the logic of multiple modules would fit into the same resource area. A suitable bus infrastructure for integrating re-configurable modules should advantageously (but not necessarily) be able to connect modules of different sizes efficiently to the rest of the system.
In [HKP06], a more flexible approach is presented that uses on-chip tristate wires in order to build a bus for re-configurable systems. This approach allows variable module sizes but necessitates tristate wires that are not found on newer FPGA architectures. In addition, [HKP06] presents four different approaches for distributing enable signals to dedicated modules connected to the bus. The first approach assigns a module to a predefined location. This is a template based methodology, where the bus interface is a fixed part in the macro infrastructure forming a tristate-based bus and where the respective module is plugged into this fixed resources. The module enable signals are distributed in a non-uniform way to particular module resources, preventing to use this approach for re-locatable modules or for multiple instances of the same module on the bus.
The second approach uses an exclusive horizontal enable signal spanning over all re-configurable slots of the FPGA for each individual module. Therefore, modules may be re-locatable but they cannot be instantiated more than once as they all would respond to the same enable signal.
The third approach compensates the disadvantage of no multiple instances of the same module by reserving extra logic resources for routing one of the horizontal enable signals to another connecting point at the same relative position for each module.
The last approach in [HKP06] utilizes a serial shift register with parallel load that is distributed over all modules with one bit in each module connecting point. The enable signal to a specific slot is distributed by shifting in a one hot encoded enable stream combined with a following load enable for the output flip-flops. These flip-flops determine which module is allowed to drive a signal onto the bus. This variant allows to access multiple instances of the same module combined with the capability of module relocation as the third approach and further saves the need of additional resources for the vertical routing of the enable signals. But this shift register enable scheme necessitates R+1 clock cycles for R resource slots provided by the bus in order to distribute a select signal to a specific module. Furthermore, this approach necessitates additional control logic inside the bus interface to make it compatible for traditional device drivers.
More related work will be presented below where we point out the advantages and novelties of the present methodology against these conventional technologies.
In view of the above, there is a need for a concept to provide an efficient communication structure on a logic chip comprising a plurality of individually addressable resource blocks.